Solid-state quantum dot devices and quantum computing using nanostructured logic gates

US6597010B2 · kind B2 · utility

Assignee

• Wisconsin Alumni Research Foundation · US

Inventors

• Mark A. Eriksson · Madison, US
• Mark G. Friesen · Middleton, US
• Robert J. Joynt · Madison, US
• Max G. Lagally · Madison, US
• Daniel W. van der Weide · Madison, US
• Paul Rugheimer · Madison, US
• Donald E. Savage · Madison, US

Key dates

• Filing date: Mar 8, 2002
• Grant date: Jul 22, 2003
• Expiry date: Mar 8, 2022

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S977/933
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Semiconductor dot devices include a multiple layer semiconductor structure having a substrate, a back gate electrode layer, a quantum well layer, a tunnel barrier layer between the quantum well layer and the back gate, and a barrier layer above the quantum well layer. Multiple electrode gates are formed on the multi-layer semiconductor with the gates spaced from each other by a region beneath which quantum dots may be defined. Appropriate voltages applied to the electrodes allow the development and appropriate positioning of the quantum dots, allowing a large number of quantum dots be formed in a series with appropriate coupling between the dots.