MOS transistor with double drain structure for suppressing short channel effect
US6597038B1 · kind B1 · utility
4Cited by
7References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 19, 1999 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Feb 19, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/917
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a semiconductor device, and a method of fabricating the same, where the semiconductor device has a gate electrode, a source-drain diffused layer of a first conductivity type, and a sidewall insulating film formed on the side face of the gate electrode, wherein the source-drain diffused layer has a lightly doped region formed below the sidewall insulating film, and a heavily doped region with impurity concentration higher than that of the lightly doped region, and the lightly doped region includes at least two kinds of impurities of the first conductivity type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.