Test bus circuit and associated method
US6597164B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2001 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Sep 27, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318533
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An on-chip test bus circuit for testing a plurality of circuits and an associated method. The test bus circuit consists of a test bus and a plurality of switching circuits which selectably provide electrical connections between the respective circuits and the test bus. The plurality of switching circuits are configured to transfer an electrical charge between a node disposed within each switching circuit not selected to provide an electrical connection and a respective charge source or sink. The charge source or sink may consist of a low-impedance, substantially noise-free DC voltage or signal source. The associated method of the present invention consists of the following steps: (1) providing a test bus; (2) providing a plurality of switching circuits for selectively providing electrical connections between the respective circuits and the test bus; (3) providing one or more charge sources or sinks coupled to the respective switching circuits; (4) setting the respective switching circuit associated with a selected one of the circuits to a conducting state; (5) setting the one or more respective switching circuits associated with the one or more unselected circuits to a non-conducti…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.