I2C repeater with voltage translation
US6597197B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1999 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Aug 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/18
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A bus repeater with voltage conversion and multiplexing circuits for use between devices with incompatible voltage levels communicating over inter-integrated circuit (I2C) buses. Bi-directional data and clock lines are passed through the circuit from one bus to the other, blocked so they are not passed on, or modified before being passed on, depending on the current transaction. The repeater is placed between two separate I2C buses and communicates between the two buses. Separating the two buses in this manner permits each bus to operate at a different voltage. Multiplexing is achieved by including logic in the repeater to recognize a first address associated with the repeater received from the first bus, and pass subsequent addresses and their associated messages through to the second bus to be decoded and processed by the devices on that bus. When the first address is not associated with the repeater, subsequent addresses and their associated messages are ignored and not passed through. To accommodate the slow-slave requirements of an I2C bus, the duration of signals on the clock line may be modified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.