System for providing electrostatic discharge protection for high-speed integrated circuits
US6597227B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2000 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Jan 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.