Integrated circuit having lithographical cell array interconnections
US6597362B1 · kind B1 · utility
10Cited by
28References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 1, 1998 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Sep 1, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A massively parallel data processing system consisting of an array of closely spaced cells where each cell has direct output means as well as means for processing, memory and input. The data processing system according to the present invention overcomes the von Neumann bottleneck of uniprocessor architectures, the I/O and memory bottlenecks that plague parallel processors, and the input bandwidth bottleneck of high-resolution displays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.