Thin film transistor substrates for liquid crystal displays including thinner passivation layer on storage capacitor electrode than other regions
US6597415B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2001 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Mar 7, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/1368
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A passivation layer is formed by coating a flowable insulating material on the substrate where a thin film transistor and a storage capacitor electrode, and a pixel electrode is formed on the passivation layer. A portion of the passivation layer is etched using the pixel electrode as a mask to make a groove on the thin film transistor, and then a black matrix is formed by filling an organic black photoresist in the groove. To increase the storage capacitance, a portion of the passivation layer is removed or to form a metal pattern on the storage capacitor electrode. A flowable insulating material is used as a gate insulating layer to planarize the substrate. In the case of the etch stopper type thin film transistor, a photo definable material is used as the etch stopper layer to reduce the parasitic capacitance between the gate electrode and the drain electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.