Content addressable memory with error detection signaling
US6597595B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2001 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Sep 18, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory (CAM) device having a data CAM array and an error CAM array. The data CAM array is provided to store data words, compare the data words with a comparand value, and, if one of the data words matches the comparand value, assert a match signal that corresponds to the matching data word. A priority encoder responds to the match signal by outputting a match address that corresponds to the matching data word. The error CAM array is provided to store at least one error address value and is coupled to the priority encoder to receive the match address. The error CAM array compares the match address with the error address value and asserts a match error signal if the match address matches the error address value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.