Memory interface using only one address strobe line
US6598116B1 · kind B1 · utility
3Cited by
7References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1999 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Nov 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for transmitting an address to a memory (3) for the purpose of reading and writing information. The memory (3) comprises memory cells for storing information as well as an address bus (19a) and a data bus (19b). Part of the address is transmitted via said address bus (19a) and part of the address is transmitted via said data bus (19b).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.