Memory device generator for generating memory devices with redundancy
US6598190B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1998 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Oct 19, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device generator for generating memory devices in a CAD environment, the generator composed of a library file containing predefined basic circuit components; memory array generation algorithm interacting with the library file for generating a variable-size memory array representation having a variable number of memory elements, and at least one redundant memory element; memory element selection circuit generation algorithm interacting with the library file for generating a memory element selection circuit to be associated with the memory array for selecting at least one memory element according to memory device address inputs. The memory element selection circuit generation algorithm having a subroutine for generating a variable-size content-addressable memory representation having a plurality of content-addressable memory locations each one associated to a respective memory element or to a redundant memory element, each of the content-addressable memory locations suitable for storing one of a set of values of the memory device address inputs and for selecting the respective memory element or redundant memory element when the memory device address inputs take the one value…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.