Technique for underfilling stacked chips on a cavity MLC module
US6599774B2 · kind B2 · utility
7Cited by
30References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2001 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Jul 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15312
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic device is provided comprising a stacked integrated circuit chip assembly wherein the top chip of the assembly is solder connected to the surface of an interconnection substrate with the other chips of the assembly being enclosed in a cavity in the interconnection substrate wherein the cavity and electrical connections of the assembly and between the substrate and top chip are sealed by supplying an encapsulant to the cavity through a through opening in the substrate which communicates with the cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.