Low temperature semiconductor layering and three-dimensional electronic circuits using the layering
US6600173B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2001 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Aug 30, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/936
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for forming a three dimensional interconnected structure, sets of devices on receiver and donor semiconductor substrates. The donor substrate is implanted with two or more exfoliating implants, the substrates are bonded together to form a bonded structure that is heated until a portion of the donor substrate exfoliates from the bonded structure and leaves a residual portion of the donor bonded to the receiver. To form three dimensional interconnected integrated circuits from devices formed on donor and receiver substrates, the receiver devices are covered with a protective and bonding layer. Interconnect structures extending from the surface of the protective and bonding layer to the devices of the receiver are formed, and a donor is implanted with two or more exfoliating implants. After bonding and heating of the two substrates until a portion of the donor exfoliates from the bonded substrates, leaving a remaining layer of the donor bonded to the receiver, the resulting devices are interconnected in an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.