Method for making low voltage transistors with increased breakdown voltage to substrate having three different MOS transistors

US6600205B2 · kind B2 · utility

Inventors

• John H. Carpenter, Jr. · Holly Springs, US
• Joseph A. Devore · Dallas, US
• Toru Tanaka · Kumamoto, JP

Key dates

• Filing date: Feb 1, 2002
• Grant date: Jul 29, 2003
• Expiry date: Feb 1, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/601

Abstract

A high-breakdown voltage transistor (30; 30′) is disclosed. The transistor (30; 30′) is formed into a well arrangement in which a shallow, heavily doped, well (44) is disposed at least partially within a deeper, more lightly-doped well (50), both formed into an epitaxial layer (43) of the substrate (42). The deep well (50) is also used, by itself, for the formation of high-voltage transistors, while the shallower well (44) is used by itself in low-voltage, high-performance transistors. This construction permits the use of high-performance, and precisely matching, transistors in high bias voltage applications, without fear of body-to-substrate (or “back-gate-to-substrate”) junction breakdown.