Input/output device having dynamic delay
US6600348B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2002 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | May 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is an input/output (IO) device for transmitting a data bit signal. In one embodiment, the IO device includes an IO device input node for receiving an input data bit signal, an IO device output node, and a common ground node. The IO device also includes a first driver having first and second n-channel FETs coupled together, first and second p-channel FETs coupled together, a plurality of third n-channel or p-channel FETs each having a drain coupled to the IO device input node, and a plurality of first capacitors coupled between the common ground node and respective sources of the plurality of third n-channel or p-channel FETs. The drains of the first p-channel FET and the second n-channel FET are coupled to the IO device output node, while the gate of the first n-channel FET is coupled to the IO device input node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.