High resolution, high speed, low power switched capacitor digital to analog converter
US6600437B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2002 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Apr 1, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switched capacitor digital to analog converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of first and second reference voltage terminals. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first and second reference voltage terminals. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal. The coupling capacitor and capacitance means have capacitances, Cs and CATT respectively, that substantially satisfy the relationship: (2p−1)·Cs−CATT=2p·C, where p is the number of bits coded in the first converter segment and C is the unit capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.