Loop antenna parasitics reduction technique
US6600452B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 29, 2001 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Nov 29, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01Q7/005
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An antenna circuit and matching technique that cancels the inductive reactance of an antenna and thereby reduces the reactive voltage of the antenna are provided. Serial tuning capacitors are inserted along the conductor of the loop antenna as often as necessary to achieve a negligible instantaneous level of reactance on the antenna. The loop antenna is broken up into loop segments, where each segment may or may not have a serial capacitor depending on the desired performance criteria. Each capacitor is selected so as to have a reactance that effectively cancels the inductive reactance of a portion of the loop segment preceding the corresponding serial capacitor. The advantage is that the instantaneous level of reactance on antenna stays nulled, and thus any reactive voltage difference between loop segments remains negligible, even with high current flowing inside the antenna. Parasitics such as ohmic losses, internal capacitive loss and capacitive loss to the external world are all reduced. Moreover, the selected serial tuning capacitors are placed along the antenna wire to effect an average reactive voltage of substantially 0 volts across the antenna. The antenna is thus balanced…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.