Clock supply circuit
US6600575B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 1999 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Jun 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N1/00
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A clock dividing section receives a system clock and generates and outputs clock signals of two or more types. Selectors select any of the clock signals of two or more types outputted by the clock dividing section and feed it to a printing control block or reading control block. A decision divider monitors operational states of each block and gives control so that a frequency to be supplied to a functional block in an idle state where any operation is not required is lower than that to be supplied to a functional block being in an active state. Power consumption of the whole custom IC can be more reduced compared with a configuration wherein a clock of fixed frequency is constantly supplied to each functional block and a noise can be controlled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.