Method to partition the physical design of an integrated circuit for electrical simulation
US6601025B1 · kind B1 · utility
5Cited by
15References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 1999 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Aug 10, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for designing an integrated circuit that includes receiving a graphical description of the integrated circuit, extracting shapes relating to a specific circuit function from the graphical description of the integrated circuit, and partitioning the extracted shapes into a plurality of segments. The method may form an electrical representation of the integrated circuit for each of the plurality of segments and solve a matrix equation (Gv=i) for each of the plurality of segments based on the electrical representation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.