Minimizing signal stub length for high speed busses
US6601125B1 · kind B1 · utility
3Cited by
7References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 17, 2000 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Mar 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package for electrically interconnecting a first bus signal path disposed on a printed circuit board and a second bus signal path disposed on the printed circuit board. The integrated circuit package may have a substrate, an integrated circuit chip die supported by the substrate. The interconnection network may be for electrically connecting the first bus signal path and the second bus signal path to a chip pad on the chip die. Thus, the first bus signal path and the second bus signal path may be electrically interconnected by only the interconnection circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.