Chip-core framework for systems-on-a-chip
US6601126B1 · kind B1 · utility
91Cited by
8References
16Claims
0Family size
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Key dates
| Filing date | May 2, 2000 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | May 2, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system-on-chip interconnection structure and method uses unidirectional buses only, central shared memory controllers, separate interconnects for high-speed and low-speed peripherals, zero wait-state register accesses, application-specific memory map and peripherals, application-specific test methodology, allowances for cache controllers, and good fits with standard ASIC flow and tools.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.