Memory interface unit with programmable strobes to select different memory devices
US6601130B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 1998 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Nov 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1694
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface unit for coupling a microprocessor to a memory external to the microprocessor. The memory comprises a plurality of memory banks of mixed type, generic memory banks such as ROM, EPROM, or the like, which are directly addressable, and DRAM memory banks, which are addressable by row and column addresses, validated by row and column strobes. The memory interface provides unique strobes for each of the memory banks, which are programmable in dependence of the type of memory bank to which a particular strobe relates. The unique strobes are programmable so as to support both generic memory and DRAM, as the case may be.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.