Method and apparatus for increasing computer performance through asynchronous memory block initialization
US6601153B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1999 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Dec 31, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99953
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for increasing processing performance in a computer system by asynchronously performing system activities that do not conflict with normal instruction processing, during inactive memory access periods. The computer system includes at least one instruction processor to process instructions of an instruction stream, and a memory to store data. One or more inactive data blocks in the memory are identified, and a list of addresses corresponding to the identified inactive data blocks is generated. Available computing cycles occurring during processing in the computer system are identified, such as processing stalls and idle memory write periods. The inactive data blocks associated with the list of addresses are initialized to a predetermined state, during the available computing cycles. Addresses corresponding to those initialized data blocks are then made available to the computing system to facilitate use of the data blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.