Method and system for branch target prediction using path information
US6601161B2 · kind B2 · utility
63Cited by
7References
24Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 30, 1998 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Dec 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for predicting a branch target for a current instruction in a microprocessor, the system comprising a cache storing indirect branch instructions and a path register. The path register is updated on certain branches by an XOR operation on the path register and the branch instruction, followed by the addition of one or more bits to the register. The cache is indexed by performing an operation on a portion of the current instruction address and the path register; the entry returned, if any, may be used to predict the target of the current instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.