Method and apparatus for debugging ternary and high speed busses
US6601196B1 · kind B1 · utility
4Cited by
8References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2000 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Nov 23, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for debugging a bus including interposing a device that monitors the data transferred between two devices on the bus such that the bus is split into two busses, with data being copied for transmission to a diagnostics device as the data is transferred between the two busses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.