Integrated circuit with a VLSI chip control and monitor interface, and apparatus and method for performing operations on an integrated circuit using the same
US6601200B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 1999 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Nov 24, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318555
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit (i.e., chip under test) includes a control and monitor interface that includes on-chip support for one or more network protocols that allow the chip to be directly coupled to a network. The control and monitor interface defines one or more operations that can be performed on the chip. In a system for testing chips under test, the control and monitor interface of all of the chips under test are coupled to a network, which is also coupled to a control and monitor mechanism. When a chip under test receives a message on the network from the control and monitor mechanism to execute an operation, it performs the requested operation, then reports the results. In this manner much of the intelligence regarding the test can be pushed on-chip, rather than having all of the testing intelligence residing in an external tester. This allows some standardization in tests that are performed from one chip under test to the next.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.