Traceback buffer management for VLSI Viterbi decoders
US6601215B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 1, 2000 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Feb 1, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4169
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This invention concerns a novel traceback memory management method and apparatus in which a memory stores Viterbi trellis state records and shifts the records in a manner so that the memory mirrors the relevant portion of the trellis accessed during the traceback for error correction and decoding. Several pointers are used so that a random access memory (RAM) can store and access the Viterbi trellis state records with only a minimum amount of hardware required to implement the memory accesses. In certain instances, where memory length is a power of 2, entire elements needed in the address generation steps are eliminated by the invention, thereby saving valuable chip area and clock cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.