Method for transistor-level calculation of the precharge time of domino logic circuits with unlocked evaluation paths
US6601220B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 1996 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Oct 22, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to the present invention, a method is provided for transistor level calculation of the precharge time of a domino logic circuit. In one version of the invention, the domino logic circuit has a plurality of cascaded stages, at least one stage having an unclocked evaluation path. In this version, the method includes the steps of determining a reset time for at least one stage of the domino circuit, determining a total reset time for the stages upstream of the at least one stage, and summing the reset time of the at least one stage with the total reset time of the cascaded stages upstream of the at least one stage to determine the precharge time. In another version, the method includes the step of performing a circuit analysis of the channel connected transistors in the at least one stage having an unclocked evaluation path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.