Semiconductor integrated circuit device including dummy patterns located to reduce dishing
US6603162B1 · kind B1 · utility
31Cited by
3References
2Claims
0Family size
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Key dates
| Filing date | Oct 20, 2000 |
| Grant date | Aug 5, 2003 |
| Priority date | — |
| Expiry date | Oct 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.