Interleaved coder and method
US6603412B2 · kind B2 · utility
45Cited by
7References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2001 |
| Grant date | Aug 5, 2003 |
| Priority date | — |
| Expiry date | Dec 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2771
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Quasi-parallel read/write interleaver architecture for data blocks by sequential spreading of variable size data subblocks into memory banks with bank address contention initiating the next data subblock. Iterative Turbo decoders with MAP decoders use such quasi-parallel interleavers and deinterleavers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.