Low complexity frequency domain equalizer having fast re-lock
US6603811B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 1998 |
| Grant date | Aug 5, 2003 |
| Priority date | — |
| Expiry date | May 29, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03668
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A low-complexity frequency domain equalizer having fast re-lock capabilities for use in a DMT transceiver. The transceiver includes a modulator that utilizes DMT modulation methods for communication over the transmission medium, a demodulator for receiving DMT signals, and a channel equalizer that operates in the frequency domain. The equalizer models the channel characteristic as an FIR filter that distorts the signal transmitted over the channel. The channel distortion is removed at the receiver by performing a de-convolution of the channel response via a frequency domain multiplication. After a period of inactivity of the receiver, the equalizer taps are updated by the use of a fast re-lock method so that the previously trained equalizer may be utilized. An undetermined sampling time offset is determined and is used to update the equalizer coefficients such that a full retraining of the equalizer is not required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.