Distribution of address-translation-purge requests to multiple processors
US6604185B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 20, 2000 |
| Grant date | Aug 5, 2003 |
| Priority date | — |
| Expiry date | Jul 20, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for deallocating memory in a multi-processor, shared memory system. In one aspect, a node in the system has a node controller that contains sequencing logic. The sequencing logic receives a command across a network. The sequencing logic translates the received command into a Purge Translation Cache (PTC) instruction and sends the PTC instruction across a bus to a processor. The processor contains bus control logic that receives the PTC instruction and purges a virtual address specified in the PTC instruction from the processor's translation lookaside buffer. By purging the virtual address, the memory is deallocated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.