Method and apparatus for accelerating instruction fetching for a processor
US6604191B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2000 |
| Grant date | Aug 5, 2003 |
| Priority date | — |
| Expiry date | Feb 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction fetching system (and/or architecture) which may be utilized by a high-frequency short-pipeline microprocessor, for efficient fetching of both in-line and target instructions. The system contains an instruction fetching unit (IFU), having a control logic and associated components for controlling a specially designed instruction cache (I-cache). The I-cache is a sum-address cache, i.e., it receives two address inputs, which compiled by a decoder to provide the address of the line of instructions desired fetch. The I-cache is designed with an array of cache lines that can contain 32 instructions, and three buffers that each have a capacity of 32 instructions. The three buffers include a Predicted (PRED) buffer that holds the instructions which are currently being executed, a NEXT buffer that holds the instructions which are to be executed after the instructions in the PRED buffer, and an ALT buffer that holds the alternate set of instructions when a branch is predicted taken/not taken and is utilized along with the PRED buffer to permit branch target retrieval within I-cache prior to a prediction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.