Arrangement and method for self-synchronization data to a local clock
US6604203B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1999 |
| Grant date | Aug 5, 2003 |
| Priority date | — |
| Expiry date | Sep 10, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0338
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An arrangement and a method for synchronizing data to a local clock. The invention incorporates a self-tested self-synchronous two-phase input port, wherein a line or an element of parallel data is tested for data read failure using two different phases or edges of the local clock. If a data read failure is detected using one phase, the other of the two phases is selected for reading the data. The arrangement includes a data read device for reading parallel elements of the data stream using one of two different phases or edges of the local clock, a data read error detecting device arranged to sample at least one element of the data stream using the two different phases or edges of the local clock, and a decision making device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.