Telecommunications system and method for supporting an incremental redundancy error handling scheme using available gross rate channels
US6604216B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2000 |
| Grant date | Aug 5, 2003 |
| Priority date | — |
| Expiry date | Feb 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0009
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A wireless communications system, transmitter, receiver and method are provided that are capable of supporting incremental redundancy error handling schemes using available gross rate channels. More specifically, the transmitter includes a coding circuit for coding a digital data block and generating a mother code word, and a reordering circuit for reordering the mother code word and generating a reordered mother code word. The transmitter also includes a modulating circuit for modulating at least one subsequence each of which has a desired number of bits taken from the reordered mother code word to fill the available bandwidth of at least one available gross rate channel. The transmitter continues to forward the modulated subsequences to the receiver until the receiver successfully decodes the digital data block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.