Method for optimizing the integrated circuit chip size for efficient manufacturing
US6604233B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2000 |
| Grant date | Aug 5, 2003 |
| Priority date | — |
| Expiry date | Dec 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70433
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The number of good IC (Integrated Circuit) chips per wafer or time to print a wafer is optimized by examining a number of prospective chip-to-wafer offsets, and, for each offset, a number of prospective arrangements of reticle exposures (shot maps). Integrating such a shot map optimization sub-system with a reticle layout (frame generation) sub-system permits creation of an optimal shot map for an IC chip of known size. These two sub-systems can also be used iteratively to explore a range of possible chip sizes, presenting the results in a simple graphical form. The instant invention integrates shot map optimization, frame generation and chip size optimization/visualization into a single system, providing the chip designer with insight into the impact of chip size on manufacturability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.