Accelerated thermal stress cycle test
US6604853B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2001 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | Oct 11, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N33/0095
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An accelerated thermal stress cycle test which can be conducted in a significantly reduced test time compared to the conventional test is provided. The test is carried out in a cluster of reaction chambers that includes a CVD chamber and a cool-down chamber such that a pre-processed wafer can be heated from room temperature to at least 350° C. in an inert gas in about 2 min., and then cooled down to not higher than 70° C. in a cool-down chamber in less than 30 sec. The heating and cooling steps can be repeated between 3 and 7 times to reveal any defect formation caused by the thermal stress cycle test. Typical defects are metal film peeling from insulating dielectric material layer or void formation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.