Zero connection for on-chip testing
US6605952B2 · kind B2 · utility
0Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2001 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | Jun 27, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R1/07314
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In order to make a connection to a test bus on a printed circuit board within a system or platform for the purpose of testing circuits within the system, a regular pattern of contact points which are coupled to the circuits to be tested are formed on the printed circuit board. The contact points are contacted with a plurality of spring loaded contacts, supported in a pattern which is the same as the pattern of contact points, with the spring loaded contacts being coupled to test equipment for testing the circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.