Structure and method for implementing wide multiplexers
US6605959B1 · kind B1 · utility
11Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2001 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | Dec 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1778
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and a structure provide in a programmable logic device wide multiplexers without increasing delay and the number of interconnections in an input routing resource over corresponding multiplexer with less number of input signals. In one embodiment, each of a number of 8-input multiplexers shares both common input signals and common selection signals with a neighboring multiplexer. Even wider multiplexers can be achieved by cascading the multiplexers in a conventional manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.