Patent · US Expired

Apparatus for biasing ultra-low voltage logic circuits

US6605981B2 · kind B2 · utility

27Cited by
14References
14Claims
0Family size

Assignee

Inventors

Key dates

Filing dateApr 26, 2001
Grant dateAug 12, 2003
Priority date
Expiry dateJun 3, 2021

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D89/213
  • WIPO fieldControl
  • WIPO sectorInstruments

Abstract

An apparatus for biasing ultra-low voltage logic circuits is disclosed. An integrated circuit device includes multiple transistors and a global body bias circuit. The global body bias circuit includes a first transistor and second transistors connected in series between a power supply and a second power supply or ground. The gate and source of the first transistor are connected to the first power supply. The gate and source of the second transistor are connected to the second power supply. The drains and bodies of the first and second transistors are connected together to form an output connected to the bodies of the other transistors within the integrated circuit device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.