High-speed current-mirror circuitry and method of operating the same
US6606001B1 · kind B1 · utility
4Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2001 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | Feb 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/372
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is disclosed high-speed current-mirror circuitry and methods of operating the same. An exemplary impedance-peaking current mirror comprises a N-channel drive transistor and a N-channel mirror transistor. The N-channel drive transistor has a source coupled to ground, a drain coupled to a current source and a gate coupled to the drain via a series connection of a resistor and an inductor. The N-channel mirror transistor has a source coupled to ground, a gate coupled to the drain of the N-channel drive transistor, and a drain coupled to a positive power supply via an impedance load.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.