True background calibration of pipelined analog digital converters
US6606042B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2002 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | May 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/442
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for performing a background calibration technique on one or more stages of a pipeline Analog-to-Digital Converter (ADC). The systems and methods employs a slow but accurate analog-to-digital converter or a slow but accurate ideal pipeline stage to correct for the residue errors in a non-ideal pipeline stage using an error function and a correction algorithm. The correction algorithm determines optimal parameters of the error function, so that the error function can be utilized to compensate for errors in the ADC. The correction algorithm and results can be applied in the digital domain or in the analog domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.