Method and apparatus for equalizing the digital performance of multiple ADC's
US6606048B1 · kind B1 · utility
60Cited by
7References
62Claims
0Family size
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Inventor
Key dates
| Filing date | Nov 16, 2000 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | Nov 16, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for equalizing the digital performance of multiple ADCs includes structure and/or steps for coupling at least one global line between the ADC's resistor ladders to allow current to flow therebetween to balance the reference voltages applied to the comparators of the ADCs. Preferably, the reference voltages are applied equally between the resistor ladders. Even more preferably, the ADC's comparators are located close to each other on a monolithic CMOS circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.