Multi-feature-size electronic structures
US6606247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2001 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | May 31, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for an electronic assembly. The electronic assembly has a first object created and separated from a host substrate. The first object has a first electrical circuitry therein. A carrier substrate is coupled to the first object wherein the first object is being recessed below a surface of the carrier substrate. The carrier substrate further includes a first carrier connection pad and a second carrier connection pad that interconnect with the first object using metal connectors. A receiving substrate, which is substantially planar, including a second electrical circuitry, a first receiving connection pad, and a second receiving connection pad that interconnect with the second electrical circuitry using the metal connectors. The carrier substrate is coupled to the receiving substrate using the connection pads mentioned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.