Disk storage subsystem with internal parallel data path and non-volatile memory
US6606589B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1999 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | Mar 2, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. The disk emulator complies with the SMD interface convention and thus to the central processor and the SMD disk controller, the disk emulator appears as a disk with virtually a zero access time. In one embodiment, the primary systems of the disk emulator are a 66-bit shift register, a parity circuit, a latch circuit, a 66-bit parallel bus and a dynamic random access memory (DRAM) array. Each of these systems interface with control systems of the disk emulator which provide the signals required for the read and write operations of the disk emulator. An error correction process is incorporated in the disk emulator which corrects single bit hard memory errors using only a single parity bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.