Multi-tiered memory bank having different data buffer sizes with a programmable bank select
US6606684B1 · kind B1 · utility
5Cited by
20References
9Claims
0Family size
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Key dates
| Filing date | Mar 31, 2000 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | Mar 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2515
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.