Unified memory system architecture including cache and directly addressable static random access memory
US6606686B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2000 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | Jan 22, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus includes a central processing unit and a memory configurable as cache memory and directly addressable memory. The memory is selectively configurable as cache memory and directly addressable memory by configuring a selected number of ways as directly addressable memory and configuring remaining ways as cache memory. Control logic inhibits indication that tag bits matches address bits and that a cache entry is the least recently used for cache eviction if the corresponding way is configured as directly addressable memory. In an alternative embodiment, the memory is selectively configurable as cache memory and directly addressable memory by configuring a selected number of sets equal to 2M, where M is an integer, as cache memory and configuring remaining sets as directly addressable memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.