Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions
US6606703B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2001 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | Jun 6, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processor and instruction conversion apparatus, including a technique for reducing the number of types of instructions and processor hardware scale when conditional instructions are used. The processor includes a stare hold unit, an obtaining unit, a decoding unit, a judging unit, and an execution unit. The judging unit judges whether a state hold unit renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction when decoded by the decoding unit. When the judgment is affirmative, the execution unit executes an operation specified by the operation code in the first conditional instruction decoded by the decoding unit. The instruction set is assigned first conditional instructions with a first state condition which is mutually exclusive with a second state condition for an unassigned second conditional instruction, both having the same operation code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.