System and method for providing error correction coding with selectively variable redundancy
US6606727B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1999 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | Oct 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/35
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method are disclosed for providing error correction coding having a selectively variable degree of redundancy. The system and method include generating extended check symbols by performing a Reed-Solomon operation on unused check symbols that do not form a portion of an interleaved code word. An extended check symbol is generated from the unused check symbols appearing in a column of the unused check symbols. The extended check symbols are stored with the interleaved code words in a data storage device. The extended check symbols are retrieved from the data storage device with the corresponding interleaved code words. Following the decoding of the interleaved code words and the identification of uncorrectable errors therein, the extended check symbols are decoded to recover the corresponding unused check symbols for the previously uncorrectable interleaved code words. The recovered unused check symbols are added to the previously uncorrectable interleaved code words so as to increase the error correcting capability thereof. The previously uncorrectable interleaved code words having the recovered unused check symbols are then decoded and errors therein corrected accordi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.