Wirebonded semiconductor package structure and method of manufacture
US6608390B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2001 |
| Grant date | Aug 19, 2003 |
| Priority date | — |
| Expiry date | Nov 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wirebonded semiconductor package structure that provides for high frequency operation, a large number of I/O terminals, controlled low impedance, compensated inductance, electromagnetic shielding against cross-talk and prevention of false signals from ground bounce includes a semiconductor device, a semiconductor package substrate and a wirebond(s) electrically connecting the semiconductor device to the semiconductor package substrate. The wirebonded semiconductor package structure also includes a first insulating encapsulant layer at least partially encapsulating the wirebond(s) and a conductor layer (e.g., a patterned gold conductor layer) disposed on the first insulating encapsulant layer and electrically connected to the semiconductor package substrate. A method for manufacturing such a wirebonded semiconductor package includes wirebonding a semiconductor device (i.e., a die) to a semiconductor package substrate to form a semiconductor package structure that includes the die, the semiconductor package substrate and a wirebond(s) electrically connecting the die to the semiconductor package substrate. A first insulating encapsulant layer is then applied that at least partially …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.