Ouput buffer circuit
US6608505B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2001 |
| Grant date | Aug 19, 2003 |
| Priority date | — |
| Expiry date | Feb 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01721
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output buffer circuit is provided, which is capable of obtaining a large drive power when the level of an input signal changes, while allowing a through current to flow in suppressed amounts. A first P-channel MOS transistor and a first N-channel MOS transistor are connected in series with a power supply. The pair of transistors are exclusively switched on and off by an input signal such that the first and second switching elements are not simultaneously on or off, to deliver an output signal corresponding to the input signal, from a common junction between the first and second switching elements. A second P-channel MOS transistor is connected in parallel with the first P-channel MOS transistor as an auxiliary transistor. A second N-channel MOS transistor is connected in parallel with the first N-channel MOS transistor as an auxiliary transistor. When the level of the input signal changes to switch one of the first P-channel MOS transistor and N-channel MOS transistor from an OFF state to an ON state, a drive switching control block delivers a signal to one of the auxiliary transistors connected in parallel with the switched one of the first P-channel MOS transistor and N-channe…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.